The present invention relates to a semiconductor memory device, and more particularly, to an address buffer of a semiconductor memory device.
FIG. 1 is a timing diagram illustrating an active operation and a read operation of a double data rate (DDR) 2 memory device.
As shown, the DDR2 memory device receives data in a DDR mode, but receives addresses and command signals in a single data rate (SDR) mode. That is, data are inputted at both a rising edge and a falling edge of a clock signal, and addresses and command signals are inputted only at a rising edge of a clock signal, just like an SDRAM.
The DDR2 memory device receiving two bank addresses BA<0:1> and fourteen addresses ADDR<0:13> are illustrated. That is, sixteen bits are used to receive the addresses, and sixteen channels and pins are required to receive the addresses.
FIG. 2 is a circuit diagram of an address buffer of a conventional semiconductor memory device.
Two address buffers 210 and 220 receiving a first address ADDR_A and a second address ADDR_B are illustrated in FIG. 2. When the semiconductor memory device uses a total of sixteen addresses as shown in FIG. 1, sixteen address buffers are required.
The first address buffer 210 includes first and second latches 211 and 212, and the second address buffer 220 includes third and fourth latches 221 and 222. The first latch 211 latches the first address ADDR_A which is inputted when the clock signal CLK is at a low level, and outputs a first latched address TLA_A. The second latch 212 latches the first latched address TLA_A which is inputted when the clock signal CLK is at a high level, and outputs a first output address LAA_A. The third latch 221 latches the second address ADDR_B which is inputted when the clock signal CLK is at a low level, and outputs a second latched address TLA_B. The fourth latch 222 latches the second latched address TLA_B which is inputted when the clock signal CLK is at a high level, and outputs a second output address LAA_B. As illustrated in FIG. 1, the addresses BA and ADDR are aligned at the center of a rising edge of the clock signal CLK. Therefore, such addresses are received when the clock signal CLK is at a low level.
An operation timing of the first and second latched addresses TLA_A and TLA_B, and the first and second output addresses LAA_A and LAA_B outputted from the first to fourth latches 211, 212, 221 and 222 is illustrated in FIG. 1.
As described above, in the conventional semiconductor memory device, since the addresses are aligned at the rising edge of the clock signal CLK and then inputted to the semiconductor memory device, the first and second address buffers 210 and 220 are designed to receive the addresses in alignment with the rising edges of the clock signal CLK.
As is well known, a test is very important in a manufacturing process of the semiconductor memory device. A test time is directly associated with a manufacturing cost. The semiconductor memory device is tested using a variety of signals applied through a test apparatus. The number of channels of the test apparatus is limited. Hence, an important issue in the semiconductor memory device is to reduce the number of channels necessary for the test.
In other words, as the number of channels or pins necessary for the test decreases, the test apparatus can test a larger number of chips at a time. This will reduce the test time and the test cost.